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- W2032664683 abstract "A low-voltage, high performance buffer suitable for implementation in standard CMOS technologies is proposed. The new buffer utilises the transient self back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 100 MHz and 0.9 V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer, with only 5% increase in power dissipation." @default.
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- W2032664683 date "1999-01-01" @default.
- W2032664683 modified "2023-09-23" @default.
- W2032664683 title "Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies" @default.
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- W2032664683 doi "https://doi.org/10.1049/el:19990116" @default.
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