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• W2032705538 abstract "This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer designed using 0.18 µm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 µW. The S-QVCO consumes 2.8 mW of power with a phase noise of −122.4 dBc/Hz at 1MHz offset." @default.
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• W2032705538 date "2012-01-01" @default.
• W2032705538 modified "2023-09-23" @default.
• W2032705538 title "A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4" @default.
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• W2032705538 doi "https://doi.org/10.1007/978-3-642-28566-0_4" @default.
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