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- W2033689471 abstract "A single loop low tracking jitter pixel clock generator is demonstrated in 28nm CMOS process. The proposed architecture only consists of a conventional single loop wide bandwidth fractional-N PLL and two synchronization skills which suppress the tracking jitter and bring out the delay control function like a DLL. When a 250MHz pixel clock is generated and synchronized with a 10kHz HSYNC, the measured tracking jitter is 9.92ps rms . The total power consumption is 9.7mW and the silicon area is only 0.010mm2 in 28nm CMOS process." @default.
- W2033689471 created "2016-06-24" @default.
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- W2033689471 date "2014-09-01" @default.
- W2033689471 modified "2023-09-25" @default.
- W2033689471 title "A 0.010mm<sup>2</sup> 9.92ps<inf>rms</inf> low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology" @default.
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- W2033689471 doi "https://doi.org/10.1109/cicc.2014.6946005" @default.
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