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- W2034193864 abstract "Timing error detection (TED) microprocessors are able to eliminate large timing margins by operating up to a voltage-frequency point in which intermittent errors occur. The detection of these errors requires an error-detection sequential (EDS) circuit. This paper presents the measurements of an EDS circuit called TEDsc. Using subthreshold source-coupled logic, TEDsc is able to dynamically adapt to system-level requirements. Measurements of TEDsc are presented in terms of a new system-level TED definition. TEDsc is implemented in 65 nm CMOS, has an area of 97.5 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , and consumes 79 pW (V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> =250 mV). TEDsc operates at a clock period (T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>CLK</sub> ) of 150 F04 at V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> =400 mV with a sufficiently large detection window. By decreasing the size of the detection window, TEDsc can operate to at least T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>CLK</sub> =50 F04." @default.
- W2034193864 created "2016-06-24" @default.
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- W2034193864 date "2011-11-01" @default.
- W2034193864 modified "2023-10-18" @default.
- W2034193864 title "Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL" @default.
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- W2034193864 doi "https://doi.org/10.1109/norchp.2011.6126746" @default.
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