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- W2034344098 abstract "The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub_block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μ C/cm2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μ C/cm2." @default.
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- W2034344098 date "2004-01-01" @default.
- W2034344098 modified "2023-09-24" @default.
- W2034344098 title "A Graded Sense-Load Scheme and Cell Data Distribution in FeRAM" @default.
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- W2034344098 doi "https://doi.org/10.1080/10584580490899316" @default.
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