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- W2034351736 abstract "A retrograde n-well is shown to be good for 1-µm bulk CMOS technology using n+polysilicon gates. P-Channel FET's with a threshold voltage of -0.6V fabricated in a retrograde n-well show small short-channel threshold lowering and good turn-off characteristics. In these devices thermally formed TiSi 2 is self-aligned to the shallow (0.3 µm) source/drain region to reduce the sheet resistance to 4 ohms/square. Because contact resistance from TiSi 2 to p+is a dominant factor in the total parasitic resistance from metal to the FET channels, high surface doping concentration of S/D regions is still preferred." @default.
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- W2034351736 date "1982-01-01" @default.
- W2034351736 modified "2023-09-25" @default.
- W2034351736 title "Design and fabrication of p-channel FET for 1-µm CMOS technology" @default.
- W2034351736 cites W2039133882 @default.
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- W2034351736 doi "https://doi.org/10.1109/iedm.1982.190393" @default.
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