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• W2034359272 abstract "Modeling parasitic parameters of Through-Silicon Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3D) Integrated Circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for capacitance of general multi-TSV structures. The error when using the closed form expressions as compared to a field solver is less than 7%. As TSV parasitic capacitance is less than other conventional IO structures' capacitance, therefore TSV technology results in lower I/O power consumption, which makes it suitable for low power applications." @default.
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• W2034359272 date "2013-07-01" @default.
• W2034359272 modified "2023-09-24" @default.
• W2034359272 title "A macro-modeling approach for through silicon via" @default.
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• W2034359272 doi "https://doi.org/10.1109/eurocon.2013.6625232" @default.
• W2034359272 hasPublicationYear "2013" @default.
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