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- W2034768247 abstract "A typical hardware development flow starts the verification process concurrently with RTL, but the overall schedule becomes limited by the effort required to complete all the necessary verification tasks. Being the limiting factor, verification schedules become unpredictable, often resulting in slippage of the tapeout dates. This paper looks at ways to restructure the flow to complete a significant part of this effort during the architectural phase of the project, prior to the start of RTL. This front-loading of the schedule allows a smaller verification team to complete the process with a tighter schedule." @default.
- W2034768247 created "2016-06-24" @default.
- W2034768247 creator A5027802666 @default.
- W2034768247 date "2009-07-26" @default.
- W2034768247 modified "2023-09-25" @default.
- W2034768247 title "Exploiting architecture for verification to streamline the verification process" @default.
- W2034768247 cites W1797377815 @default.
- W2034768247 doi "https://doi.org/10.1145/1629911.1629970" @default.
- W2034768247 hasPublicationYear "2009" @default.
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