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- W2034962526 abstract "Abstract In this paper we present a translation from high-level specifications written in the formal description technique LOTOS to hardware descriptions in the standard language VHDL. The objective is to use the formal foundation of LOTOS in order to improve the design phase of hardware components. VHDL is used as an intermediate step, taking advantage of the existing simulation and synthesis tools. The translation methodology proposed in this paper has required the extension of LOTOS with timing features and will be supported by automatic tools, that are already under development." @default.
- W2034962526 created "2016-06-24" @default.
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- W2034962526 date "1993-09-01" @default.
- W2034962526 modified "2023-10-01" @default.
- W2034962526 title "VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project" @default.
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- W2034962526 doi "https://doi.org/10.1016/0165-6074(93)90199-u" @default.
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