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• W2035575158 abstract "This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM --- attributed to PCM SET --- by proposing a novel PCM memory architecture that integrates WOM-codes at the memory organization and memory controller levels. The proposed 2/3 WOM-code PCM architecture is able to reduce memory write (read) latency by 20.1% (10.2%) on average across general-purpose (SPEC CPU2006), embedded (MiBench), and high-performance (SPLASH-2) benchmarks. To further improve the write latency of WOM-code PCM, we propose a PCM-refresh approach that uses idle cycles to preemptively set PCM rows to the initial WOM-code state. Results show that WOM-code PCM with PCM-refresh can reduce memory write (read) latency by 54.9% (47.9%) on average across the benchmarks. Finally, to balance write latency improvements against WOM-code PCM overhead, we propose a WOM-code cached PCM (WCPCM) architecture that uses WOM-code PCM as the cache alongside conventional PCM main memory. For just 4.7% memory overhead, WCPCM reduces memory write (read) latency by 47.2% (44.0%) on average across the benchmarks." @default.
• W2035575158 created "2016-06-24" @default.
• W2035575158 creator A5021693439 @default.
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• W2035575158 date "2014-03-24" @default.
• W2035575158 modified "2023-09-23" @default.
• W2035575158 title "Write-once-memory-code phase change memory" @default.
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• W2035575158 doi "https://doi.org/10.5555/2616606.2616829" @default.
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