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- W2036702473 abstract "This paper deals with the implementation of parallel processing SPWM multilevel techniques through programmable gate arrays (Field Programmable Gate Arrays, FPGAs). It is shown that switching losses in power converters significantly decreases with an increased number of levels in the SPWM signal, thus providing an efficient energy transfer. The multilevel SPWM control response of 3, 9 and 21 levels in VHDL through the FPGA Xilinx Spartan family is illustrated." @default.
- W2036702473 created "2016-06-24" @default.
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- W2036702473 date "2013-09-01" @default.
- W2036702473 modified "2023-10-18" @default.
- W2036702473 title "Generation of a multilevel SPWM technique of 3, 9 and 21 levels with FPGAs" @default.
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- W2036702473 doi "https://doi.org/10.1109/naps.2013.6666843" @default.
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