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• W2036707538 abstract "It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC'99 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill." @default.
• W2036707538 created "2016-06-24" @default.
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• W2036707538 date "2011-11-01" @default.
• W2036707538 modified "2023-10-18" @default.
• W2036707538 title "Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling" @default.
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• W2036707538 doi "https://doi.org/10.1109/ats.2011.35" @default.
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