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- W2037402731 abstract "In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline. Two-level parallel processing approach makes the decoder operate in real-time for high-performance applications. The demonstration on FPGA prototype board shows the efficiency of the proposed scalable architecture achieved by multi-core design. The system is estimated to be able to decode UHD video coded by HEVC in real-time." @default.
- W2037402731 created "2016-06-24" @default.
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- W2037402731 date "2014-07-01" @default.
- W2037402731 modified "2023-09-27" @default.
- W2037402731 title "Multi-core based HEVC hardware decoding system" @default.
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- W2037402731 doi "https://doi.org/10.1109/icmew.2014.6890626" @default.
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