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- W2037751012 abstract "We hereby report the design and measurements of a 101–118 GHz 65 nm CMOS transmitter. The transmitter architecture is based on a two-step upconversion using a single 80 GHz LO with the quadrature phases generated by injection locked frequency dividers. Both BPSK and QPSK modulations with a maximum datarate of 20.6 Gbps are supported. A measured output power of −5 dBm at 115 GHz and an error-vector magnitude of 17.5% for 30 dB conversion-loss downconversion link are obtained. The chip core area is 0.21 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and a DC power consumption of 280 mW." @default.
- W2037751012 created "2016-06-24" @default.
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- W2037751012 date "2014-06-01" @default.
- W2037751012 modified "2023-10-16" @default.
- W2037751012 title "An F-band 20.6Gbp/s QPSK transmitter in 65nm CMOS" @default.
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- W2037751012 doi "https://doi.org/10.1109/rfic.2014.6851725" @default.
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