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- W2038076822 abstract "An ultrathin junctionless (JL) charge trap flash (CTF) thin-film transistor (TFT) with a sub-2 nm thick poly-Si channel is demonstrated for 3D stacked flash memory. It provides the excellent memory performance of faster program/erase (P/E) speed, larger memory window (>12 V), and better endurance (>10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>4</sup> cycles) than inversion-mode (IM) devices; this device also has excellent 10-year data retention at 150 °C, as well as improved on/off current ratio (>10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>8</sup> ) and subthreshold swing (SS). The transfer characteristics and the memory performance as a function of the poly-Si channel thickness (T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Ch</sub> ) are also systematically investigated." @default.
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- W2038076822 date "2014-06-01" @default.
- W2038076822 modified "2023-09-27" @default.
- W2038076822 title "Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications" @default.
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- W2038076822 doi "https://doi.org/10.1109/vlsit.2014.6894385" @default.
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