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- W2038479357 abstract "In this paper a self-oscillating ΣΔ modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator. A second order CMOS prototype was constructed in a 0.18 μm technology. A clock frequency of 850 MHz generates a self-oscillation mode at 106.25 MHz. The modulator achieves a dynamic range (DR) of 66 dB for a signal bandwidth of 5 MHz. The power consumption is only 6 mW and the chip area of the modulator core is 0.025 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
- W2038479357 created "2016-06-24" @default.
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- W2038479357 date "2010-09-01" @default.
- W2038479357 modified "2023-10-16" @default.
- W2038479357 title "5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025mm<sup>2</sup>" @default.
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- W2038479357 doi "https://doi.org/10.1109/cicc.2010.5617589" @default.
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