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• W2039231323 abstract "Hardware software co-synthesis process intends to determine an optimal architecture for an embedded application specified by a task graph or a specification language. In this paper, we present a co-synthesis approach targeting MPSoCs and distributed memory multiprocessor architectures for high performance embedded applications. Our co-synthesis approach produces pipelined multiprocessor architectures consisting of heterogeneous processing elements connected by a point-to-point communication structure. The co-synthesis process consists of four distinct phases; processing element selection for addition to the system, pipelined task allocation, scheduling and a regular interconnection topology mapping. Initially, an irregular topology is generated that is mapped to a regular architecture. Our co-synthesis methodology performs system partitioning and produces an irregular topology multiprocessor system. It also generates an optimal (or sub-optimal) regular topology architecture after considering some of the well-known regular topologies like mesh, hypercube, tree, etc. The co-synthesis method is demonstrated by exploring embedded architectures for MPEG encoder and artificially generated application task graphs representing complex embedded systems." @default.
• W2039231323 created "2016-06-24" @default.
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• W2039231323 date "2008-10-08" @default.
• W2039231323 modified "2023-10-01" @default.
• W2039231323 title "CAD tool for hardware software co-synthesis of heterogeneous multiple processor embedded architectures" @default.
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• W2039231323 doi "https://doi.org/10.1007/s10617-008-9031-1" @default.
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