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- W2039355816 abstract "We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, V DS , and gate voltage, V g . Also, the effect of bulk and surface adatom in the wire cross section was evaluated." @default.
- W2039355816 created "2016-06-24" @default.
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- W2039355816 date "2011-03-01" @default.
- W2039355816 modified "2023-09-24" @default.
- W2039355816 title "Atomic scale simulation of a junctionless silicon nanowire transistor" @default.
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- W2039355816 doi "https://doi.org/10.1109/ulis.2011.5757980" @default.
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