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- W2040242807 abstract "In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used." @default.
- W2040242807 created "2016-06-24" @default.
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- W2040242807 date "2012-10-01" @default.
- W2040242807 modified "2023-10-16" @default.
- W2040242807 title "Design and implementation of floating point multiplier based on Vedic Multiplication Technique" @default.
- W2040242807 cites W2148116469 @default.
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- W2040242807 doi "https://doi.org/10.1109/iccict.2012.6398204" @default.
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