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• W2040743375 abstract "Fast and efficient reduction circuits are critical for a broad range of scientific and embedded system applications. High throughput reduction circuits are typically hand designed for specific vector lengths. These circuits need to be modified when the set lengths are changed. In this paper, we present a new design approach that can handle any set length or combination of different consecutive set lengths without stalling and generates in-order results. The flexibility of the design allows it to be used for any reduction operations, such as floating-point addition and multiplication. By providing a simple and efficient interface to the user and a modular architecture for the designer, the proposed technique has a broad impact across a wide range of custom hardware designs." @default.
• W2040743375 created "2016-06-24" @default.
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• W2040743375 date "2013-09-01" @default.
• W2040743375 modified "2023-09-25" @default.
• W2040743375 title "Modular Design of Fully Pipelined Reduction Circuits on FPGAs" @default.
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• W2040743375 doi "https://doi.org/10.1109/tpds.2012.267" @default.
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