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- W2040896689 abstract "Beside all the advantages of continuous-time (CT) delta-sigma modulators (ΔΣMs) like higher sampling rate/bandwidth, lower thermal noise, self antialiasing filtering and lower power consumption, they are severely suffer from clock-jitter in their feedback's at the digital to analogue converter (DACs) point. In this paper, a novel technique and method is presented to reduce the effect of clock-jitter in switched-current (SI) DACs and in particular for the CT ΔΣM applications. Unlike the switched-capacitor (SC) DAC approach, applying the proposed technique (switched shaped-current (SSI)) does not introduce extra demands on the modulator and does not increase its power consumption and is fully compatible with CMOS processes and single-bit/multi-bit operations which are widely used in high speed applications. Circuit-level simulations showed very high levels of immunity of the proposed technique to clock-jitter." @default.
- W2040896689 created "2016-06-24" @default.
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- W2040896689 date "2005-01-01" @default.
- W2040896689 modified "2023-10-17" @default.
- W2040896689 title "A digital to analogue converter with enhanced immunity to clock jitter" @default.
- W2040896689 doi "https://doi.org/10.1049/cp:20050175" @default.
- W2040896689 hasPublicationYear "2005" @default.
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