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• W2041646453 abstract "A novel time borrowing method called dynamic Flip-Flop conversion is presented in this paper. A timing violation predictor detects the violations halfway in the critical path and dynamically converts the critical Flip-Flop to a latch. This way, time borrowing benefits of latches are utilized in a Flip-Flop based design which is more adaptable with Computer-Aided-Design tools. The overhead of this method is smaller than that of similar methods due to the elimination of delay elements. According to the post-synthesis simulations and Monte-Carlo analysis of Spice simulations on some ITC'99 benchmark circuits, the power overhead of the proposed method is about 15% and 19% smaller than that of Soft-Edge-Flip-Flop and Dynamic-Clock-Stretching circuits respectively in a simple case of about 40% yield improvement. This overhead would be relatively even smaller for higher performance and yield improvements." @default.
• W2041646453 created "2016-06-24" @default.
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• W2041646453 date "2014-03-24" @default.
• W2041646453 modified "2023-09-23" @default.
• W2041646453 title "Dynamic flip-flop conversion to tolerate process variation in low power circuits" @default.
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• W2041646453 doi "https://doi.org/10.5555/2616606.2616742" @default.
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