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- W2042621414 abstract "This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision multiplier achieves an improvement of 25.5% in delay and up to 29% reduction of power-delay product when compared to existing designs." @default.
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- W2042621414 date "2012-12-01" @default.
- W2042621414 modified "2023-09-27" @default.
- W2042621414 title "A Modified Twin Precision Multiplier with 2D Bypassing Technique" @default.
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- W2042621414 doi "https://doi.org/10.1109/ised.2012.58" @default.
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