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- W2042667731 abstract "As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory and IO defects and associated test and validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, a reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected to detect memory and IO defects, and combined with the software assisted repair technology to automatically repair memory cell defects on 3D stacked Wide-IO DRAM. Additionally, we also present the CPGC gate count, power, simulation, and silicon results. The reusable CPGC IP is designed to connect to a standard IP interface, which enables a quick turn-key SOC development cycle. Silicon results show CPGC can speed up validation by 5x, improve test time from minutes down to seconds, and decrease debug time by 5x including root-cause of boot failures of the memory interface. CPGC is also used in memory training and initialization, which makes it a critical part of Intel SOC." @default.
- W2042667731 created "2016-06-24" @default.
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- W2042667731 date "2014-10-01" @default.
- W2042667731 modified "2023-09-27" @default.
- W2042667731 title "A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time" @default.
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- W2042667731 doi "https://doi.org/10.1109/test.2014.7035340" @default.
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