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- W204303334 abstract "Multiply and accumulate function is the important part of digital signal processing algorithms. This can be implemented more effectively with distributed arithmetic (DA) architecture [1]. These architectures make extensive use of look-up tables, which make them ideal for implementing digital signal processing functions on Xilinx FPGAs. An emerging arithmetic-intensive digital signal processing algorithm is the discrete wavelet transform (DWT) which have proven to be extremely useful for image and video coding applications like MPEG-4 and JPEG 2000[2]. But the limitation of this architecture is that the size of look-up tables get increased exponentially as the constant coefficients of wavelet used for these applications increases. In this paper, we proposed a novel methodology to implement the Burrows wheeler transform (BWT) [3] block in FPGA for achieving memory reduced DA." @default.
- W204303334 created "2016-06-24" @default.
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- W204303334 date "2012-01-01" @default.
- W204303334 modified "2023-10-06" @default.
- W204303334 title "VLSI Implementation of Burrows Wheeler Transform for Memory Reduced Distributed Arithmetic Architectures" @default.
- W204303334 cites W2095603848 @default.
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- W204303334 doi "https://doi.org/10.1007/978-3-642-35615-5_36" @default.
- W204303334 hasPublicationYear "2012" @default.
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