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• W2043104325 abstract "This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 µW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation." @default.
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• W2043104325 date "2015-01-01" @default.
• W2043104325 modified "2023-09-26" @default.
• W2043104325 title "A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications" @default.
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• W2043104325 doi "https://doi.org/10.1109/jssc.2014.2371454" @default.
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