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• W2043809591 abstract "This brief proposes a low-power architecture for a discrete-time (DT) delta-sigma modulator to take full advantages of increased quantization levels. In the proposed architecture, noise-shaped segmentation is applied to both the quantizer and the feedback digital-to-analog converter to maintain a high resolution and a high linearity and, at the same time, keep the hardware complexity low. This leads to a significantly reduced output swing of the integrator to minimize the slewing-related distortion in a DT implementation. The resulting uniform linear settling behavior can tolerate a relatively large settling error without degrading the performance, which greatly relaxes the bandwidth requirement of the op-amp design. The reduced output swing also allows the use of low-gain amplifiers, which is particularly attractive for an advanced technology in which the intrinsic gain of the transistor is degraded. The proposed architecture is analyzed and verified through simulation." @default.
• W2043809591 created "2016-06-24" @default.
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• W2043809591 date "2015-03-01" @default.
• W2043809591 modified "2023-09-24" @default.
• W2043809591 title "A Multibit Delta–Sigma Modulator With Double Noise-Shaped Segmentation" @default.
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• W2043809591 doi "https://doi.org/10.1109/tcsii.2014.2368261" @default.
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