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• W2044196265 abstract "A novel realization of a switched-capacitor (SC) integrator is proposed. The integrator attenuates the input during both clock phases, so that the time constant of the integrator is realized with the product of two capacitance ratios instead of a single capacitance ratio. The capacitance spread only increases as the square root of the time constant. This integrator is stray-insensitive. The influence of the finite DC-amplifier gain and dynamic settling is the same as in conventional SC integrators. A low-pass notch SC biquad is presented as an example to show the capacitance advantage of the integrator. The example also shows that the increase of amplifier offset is small if the total offset of the entire SC filter is considered. It is shown that the SC low-pass notch biquad reduces the total capacitance by a factor of more than three.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
• W2044196265 created "2016-06-24" @default.
• W2044196265 creator A5084082009 @default.
• W2044196265 date "1989-01-01" @default.
• W2044196265 modified "2023-10-01" @default.
• W2044196265 title "A novel technique for the reduction of capacitance spread in high-Q SC circuits" @default.
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• W2044196265 doi "https://doi.org/10.1109/31.16574" @default.
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