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• W2044674552 abstract "As microprocessor chips integrate a growing number of cores, the issue of interconnection becomes more important for overall system performance and efficiency. Compared to traditional distributed shared-memory architecture, chip-multiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. For example, the advantage of off-the-shelf interconnect and the in-field scalability of the interconnect are less important in a chip-multiprocessor. On the other hand, even with worsening wire delays,packet switching represents a non-trivial component of overall latency." @default.
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• W2044674552 date "2011-06-04" @default.
• W2044674552 modified "2023-10-18" @default.
• W2044674552 title "A case for globally shared-medium on-chip interconnect" @default.
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• W2044674552 doi "https://doi.org/10.1145/2000064.2000097" @default.
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