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- W2044728745 abstract "The mainstreaming of chip multiprocessor (CMP) architectures exact a profound impact on valuable resources, for example, L3 cache capacity, off-chip bandwidth and on-board main memory capacity. Even with latency-hiding software strategies, in a memory-starved system, a processor can remain idle for several decades of clock cycles and performance will degrade [1]. Two hardware solutions are being developed for opening the memory bottleneck; (1) Stack bare SRAM die memory, with multiplexer-demultiplexer, using through-silicon vias and place the SRAM stacks around the multi-core processor at the multi-chip carrier level [2] to increase L3 capacity and, in addition, also stack dynamic random access memory (DRAM) dies on board to increase main memory capacity needed for numerically intensive and storage intensive computations." @default.
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- W2044728745 date "2010-08-01" @default.
- W2044728745 modified "2023-09-22" @default.
- W2044728745 title "Millimeter-wave main memory-to-processor data bus" @default.
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- W2044728745 doi "https://doi.org/10.1109/icept.2010.5582788" @default.
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