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• W2044851785 abstract "L1 instruction fetch misses remain a critical performance bottleneck, accounting for up to 40% slowdowns in server applications. Whereas instruction footprints typically fit within last-level caches, they overwhelm L1 caches, whose capacity is limited by latency constraints. Past work has shown that server application instruction miss sequences are highly repetitive. By recording, indexing, and prefetching according to these sequences, nearly all L1 instruction misses can be eliminated. However, existing schemes require impractical storage and considerable complexity to correct for minor control-flow variations that disrupt sequences." @default.
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• W2044851785 date "2013-12-07" @default.
• W2044851785 modified "2023-10-17" @default.
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• W2044851785 doi "https://doi.org/10.1145/2540708.2540731" @default.
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