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- W2045117152 abstract "In this work, we investigate the possibility of achieving low V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>T</sub> nMOS FinFETs with single metal gate by using a dysprosium oxide (Dy <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> O <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> ) cap layer inserted between gate dielectric and metal. We determine an optimum ratio between Dy <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> O <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> and SiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> gate dielectric thicknesses for low nMOS V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>T</sub> with good process margin and no loss in performance and reliability." @default.
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- W2045117152 date "2007-10-01" @default.
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- W2045117152 title "Metal Gate Technology using a Dy<inf>2</inf>O<inf>3</inf> Dielectric Cap Approach for multiple-V<inf>T</inf> in NMOS FinFETs" @default.
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- W2045117152 doi "https://doi.org/10.1109/soi.2007.4357892" @default.
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