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- W2045563143 abstract "An efficient optimized area and speed FPGA implementation for the Advanced Encryption Standard is proposed in this paper. The iterative looping method is adopted with multistage sub-pipelining architecture to achieve a 1.33 Gbps throughput for the AES-128 bit Encryption process. The proposed design operates at 425 MHz with 303 CLB slices on a Xilinx Virtex-5 XC5VLX50 FPGA Device. For real-time hardware evaluation, an end-user Java based application is developed. The software application is linked to the hardware design through the Xilinx MicroBlaze soft processor core." @default.
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- W2045563143 date "2013-09-01" @default.
- W2045563143 modified "2023-10-18" @default.
- W2045563143 title "Real-time efficient FPGA implementation of aes algorithm" @default.
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- W2045563143 doi "https://doi.org/10.1109/socc.2013.6749688" @default.
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