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- W2045583681 abstract "In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology." @default.
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- W2045583681 date "2013-12-01" @default.
- W2045583681 modified "2023-10-16" @default.
- W2045583681 title "A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology" @default.
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- W2045583681 doi "https://doi.org/10.1109/iedm.2013.6724745" @default.
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