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• W2045597921 abstract "Test is an essential task since the early days of digital circuits. Every produced chip undergoes at least a production test supported by on-chip test infrastructure to reduce test cost. Throughout the technology evolution fault tolerance gained importance and is now necessary in many applications to mitigate soft errors threatening consistent operation. While a variety of effective solutions exists to tackle both areas, test and fault tolerance are often implemented orthogonally, and hence do not exploit the potential synergies of a combined solution. The unified architecture presented here facilitates fault tolerance and test by combining a checksum of the sequential state with the ability to flip arbitrary bits. Experimental results confirm a reduced area overhead compared to a orthogonal combination of classical test and fault tolerance schemes. In combination with heuristically generated test sequences the test application time and test data volume are reduced significantly." @default.
• W2045597921 created "2016-06-24" @default.
• W2045597921 creator A5008775226 @default.
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• W2045597921 date "2014-03-24" @default.
• W2045597921 modified "2023-09-26" @default.
• W2045597921 title "Bit-flipping scan - a unified architecture for fault tolerance and offline test" @default.
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• W2045597921 doi "https://doi.org/10.5555/2616606.2616843" @default.
• W2045597921 hasPublicationYear "2014" @default.
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