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• W2047560179 abstract "Networks-on-Chip (NoC) gradually becomes a main contributor of chip-level power consumption. Due to the temporal and spatial heterogeneity of on-chip traffic, existing power management approaches cannot adapt the NoC power consumption to its traffic intensity, and hence lead to a suboptimal power efficiency. They either resort to over-provisioned NoC design that only suits for traffic spatial distribution, or coarse-grained power gating that only serves traffic temporal variation. In this paper, we propose a novel NoC architecture called Shuttle Networks-on-Chip (ShuttleNoC). By permitting packets shuttling between multiple subnetworks, localized power adaptation can be achieved. Experimental results show that ShuttleNoC could achieve optimal power efficiency with up to 23.5% power savings and 22.3% performance boost in comparison with traditional heterogeneity-agnostic NoC designs." @default.
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• W2047560179 date "2015-01-01" @default.
• W2047560179 modified "2023-10-16" @default.
• W2047560179 title "ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation" @default.
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• W2047560179 doi "https://doi.org/10.1109/aspdac.2015.7058995" @default.
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