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- W2048260265 abstract "It is well known that the in-plane distortion induced in a process could limit the overlay performance of lithographic tools. In the submicron lithography with ever increasing trend for high packing density, the capability of the lithographic tool to compensate for such distortions becomes increasingly important because of the stringent overlay budget. The in-plane distortion of 4 inch silicon wafers in a submicron CMOS process of a 1Mbit SRAM device was measured directly using the laser interferometer controlled stepping stage of in-house built PHILIPS submicron stepper known as SIRE-3. The slice diameter was measured at every masking step on wafer to wafer and lot to lot basis. The maximum change in slice diameter was measured to be 0.6 μm over 90 mm between Field Oxide masking level and Poly masking level. No significant misregistration was observed between these two masking steps, in spite of the fact that the exposure system used did not have wafer to wafer magnification control. Nevertheless, such wafer expansions have to be taken into account in the overall overlay budget in a process. It is expected that the automatic wafer to wafer magnification control feature of the commercial version of this stepper (PAS2500) could effectively compensate for such in-plane distortions and reduce the misregistration budget of the high density circuits." @default.
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- W2048260265 date "1989-05-01" @default.
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- W2048260265 title "In-plane distortion in silicon wafers induced by a submicron CMOS process" @default.
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- W2048260265 doi "https://doi.org/10.1016/0167-9317(89)90100-7" @default.
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