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- W2048528097 abstract "Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO 2 /TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ~20% higher electron and hole mobility than literature data on optimized SiO x /HfO 2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level." @default.
- W2048528097 created "2016-06-24" @default.
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- W2048528097 date "2014-08-12" @default.
- W2048528097 modified "2023-10-03" @default.
- W2048528097 title "Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs" @default.
- W2048528097 doi "https://doi.org/10.1149/06406.0249ecst" @default.
- W2048528097 hasPublicationYear "2014" @default.
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