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- W2048578429 abstract "Compared with general Single-core systems, Multi-core systems not only have higher computing capabilities and lower power consumption but also bring high-throughput and high-parallel challenges to the communication on the chip. Depending on the design of traditional 2D-mesh Network on Chip (NoC), this paper researches a Dual-port NoC (DPN), which further enhances the parallelism of multi-core systems, such that each resource node can send or receive two-way data at the same time. Under streaming mode, this design can make every resource do binary operation to improve system's efficiency. This paper designs and implements a 4X4 DPN on FPGA. This paper also tests throughput and flit latency of DPN and traditional 2D-mesh in different package length and sending interval. The results of tests show that throughput has increased %46.4 in average while flit latency has increased %16.5 in average." @default.
- W2048578429 created "2016-06-24" @default.
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- W2048578429 date "2014-10-01" @default.
- W2048578429 modified "2023-09-27" @default.
- W2048578429 title "Design and implementation of Dual-port Network on Chip" @default.
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- W2048578429 doi "https://doi.org/10.1109/icsict.2014.7021161" @default.
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