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- W2048946481 abstract "In the design procedure of system on chip (SoC), it is needed to make use of hardware-software co-design technique owing to the great complexity of SoC. One of main steps in hardware-software co-design is how to carry out the partitioning of a system into hardware and software components. The efficient approaches for hardware-software partitioning can achieve good system performance, which is superior to the techniques that use software only or use hardware only. In this paper, a method based on neural networks is presented for the hardware-software partitioning of system on chip. The discrete Hopfield neural networks corresponding to the problem of hardware-software partitioning is built, the states of neural neurons are able to represent whether the required components or functionalities are to be implemented in hardware or software. An algorithm based on the principle of simulated annealing is designed, which can be used to compute the minimal energy states of neural networks, therefore the optimal partitioning schemes are obtained. The experimental results show that the hardware-software partitioning method proposed in this paper can obtain the near optimal partitioning for a lot of example circuits." @default.
- W2048946481 created "2016-06-24" @default.
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- W2048946481 date "2011-08-25" @default.
- W2048946481 modified "2023-10-17" @default.
- W2048946481 title "Hardware-software partitioning for the design of system on chip by neural network optimization method" @default.
- W2048946481 doi "https://doi.org/10.1117/12.904816" @default.
- W2048946481 hasPublicationYear "2011" @default.
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