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- W2049271787 abstract "In this paper, we describe the simulation technology used to estimate soft errors in logic circuits. The neutron induced soft-error simulator (NISES), which was previously developed for estimating soft-errors in memories is applied to the estimating soft errors in latch circuits and its effectiveness is shown. We model soft-error phenomena in combinational circuits and develop a novel simulation system for estimating soft errors in such circuits. Estimated results show that soft-error rate increases in combinational circuits as technology advances. Soft errors in logic circuits will thus become crucial." @default.
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- W2049271787 date "2006-04-25" @default.
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- W2049271787 title "Neutron-Induced Soft-Error Simulation Technology for Logic Circuits" @default.
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- W2049271787 doi "https://doi.org/10.1143/jjap.45.3256" @default.
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