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• W2051393471 abstract "In this paper, a 2-D forward discrete cosine transform (FDCT) and inverse DCT (IDCT) core are presented. The proposed DCT core uses a single 1-D transform core and a transpose memory in order to achieve an area-efficient design. By exploiting the even and odd symmetrical properties of the FDCT and IDCT computations, the DCT core can share hardware resources. Furthermore, first-dimensional (1st-D) and second-dimensional (2nd-D) operations can be run simultaneously (1st-D FDCT, 2nd-D FDCT, 1st-D IDCT, 2nd-D IDCT) in the proposed 1-D core by using the proposed time division strategy, which shares hardware resources achieving a high-throughput design. Measurement results show that the DCT core achieves a throughput of 250 MP/s when simultaneously operating FDCT and IDCT, consuming only 19650 logic gates when fabricated using the TSMC 0.18-μm CMOS process. The DCT core achieves superior hardware efficiency compared to the existing cores." @default.
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• W2051393471 date "2014-11-01" @default.
• W2051393471 modified "2023-10-05" @default.
• W2051393471 title "A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy" @default.
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• W2051393471 doi "https://doi.org/10.1109/tvlsi.2013.2290136" @default.
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