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- W2053008268 abstract "We report on aggressively scaled replacement metal gate, high- k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high- k deposition thermal (PDA) and plasma (SF 6 ) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage ( J G ) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF 6 , without equivalent oxide thickness (EOT) penalty; 2) SF 6 enables improved mobility and reduced interface trapped charge density ( N it ) down to narrower fin devices [fin width ( W Fin ) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage | V T |, and substantially improved reliability behavior due to reduction of bulk defects." @default.
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- W2053008268 date "2014-03-17" @default.
- W2053008268 modified "2023-10-01" @default.
- W2053008268 title "Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-klast devices and enabling a simplified scalable CMOS integration scheme" @default.
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- W2053008268 doi "https://doi.org/10.7567/jjap.53.04ea04" @default.
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