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- W2053923310 abstract "The performance and reliability of submicron CMOS circuits have been affected by hot-carrier stress induced degradation. Three common forms of CMOS latch circuits designed using a 0.7-micron commercial process have been considered in a comparative study of the stress levels experienced by individual devices in the circuit. Average stress levels on all the devices over a typical simulation cycle was used to assess the life-time and the reliability of the circuits. We describe a technique that was used to identify the devices having higher than normal stress which may consequently degrade at a faster rate than other devices leading to an early failure of the circuit. We have developed design techniques that can be used to reduce the stress levels in identified devices. The improvements in life-time and reliability have been assessed and analysed. The best circuit configuration to reduce hot-carrier stress induced degradation has been identified." @default.
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- W2053923310 date "1998-06-01" @default.
- W2053923310 modified "2023-09-27" @default.
- W2053923310 title "Improved reliability of bistable circuits by selective hot-carrier stress reduction" @default.
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- W2053923310 doi "https://doi.org/10.1016/s0026-2714(98)00084-5" @default.
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