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- W2054649748 abstract "The logical architecture for this effort was developed at Wright Laboratory. Oak Ridge National Laboratory has taken the design and reordered the data flow to allow a physical architecture to be prototypes using DSP chips, transputers, or VLSI. The design allows image algebra operations to be executed in a staged pipeline at nearly the same throughput as a memory to memory transfer. The control is by direct memory access from the host, in this case a SUN SPARC II. Reduce operations such as sum, maximum, and minimum are captured as by-products of the pipeline operation." @default.
- W2054649748 created "2016-06-24" @default.
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- W2054649748 date "1993-06-23" @default.
- W2054649748 modified "2023-10-09" @default.
- W2054649748 title "<title>Prototype coprocessor for image algebra operations</title>" @default.
- W2054649748 doi "https://doi.org/10.1117/12.146670" @default.
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