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• W2054716548 abstract "The 12-core 649mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>t</inf> s are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5–80nm, 2–144nm, 3–288nm, and 3–640nm pitch layers for low-latency communication as well as 2–2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks." @default.
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• W2054716548 date "2014-02-01" @default.
• W2054716548 modified "2023-10-11" @default.
• W2054716548 title "5.1 POWER8^TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth" @default.
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• W2054716548 doi "https://doi.org/10.1109/isscc.2014.6757353" @default.
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