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- W2055146521 abstract "An SRC, sampling rate converter, consisting of conventional filter-type SRC and time-domain SRC using Fourier interpolation algorithm is proposed. Filter portion realizes over-sampling, and its output is interpolated by the Fourier portion. The SRC achieves noise level of as low as -110dB for all frequencies, and its gate count is about 1000000 FPGA logic cells" @default.
- W2055146521 created "2016-06-24" @default.
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- W2055146521 date "2006-05-01" @default.
- W2055146521 modified "2023-09-25" @default.
- W2055146521 title "Hybrid Sample Rate Converter with 110dB SNR and 1/10 Less Logic Gates" @default.
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- W2055146521 doi "https://doi.org/10.1109/eit.2006.252121" @default.
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