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• W20554705 abstract "SiC is an attractive semiconductor for fabricating high power metal-oxide-semiconductor (MOS) devices because of its high breakdown field and high thermal conductivity. In addition, like silicon, SiC has a natural advantage for fabricating MOS devices because high quality SiO2 for gate insulators can be thermally grown directly on the SiC in an oxidizing ambient. Despite these potential advantages, experimental SiC MOS devices today have poor performance and abnormally low conductance. This is particularly a problem in 4H- compared to 6H-SiC, although 4H is the preferred polytype for power devices because of its higher electron mobility. It was proposed initially that the low conductance arises from extreme SiC surface roughness [1] or segregation of aluminum dopant atoms at the SiC/SiO2 interface from the p-type SiC substrate [2, 3]. It is generally recognized now that the low conductance is actually due to a high density of electron traps D it at the SiC/SiO2 interface [1, 4, 5]. These traps reduce the conductance by two approximately equal effects: (1) many electrons are trapped by the defects and are not free to contribute to the drain current, and (2) the mobility of the remaining free electrons is reduced by Coulomb scattering from all the trapped electrons. The traps are believed to arise from two physical mechanisms: near-interfacial traps in the oxide caused by oxygen deficiencies, and clusters of graphite-like excess carbon at the interface released by the oxidation process [4]." @default.
• W20554705 created "2016-06-24" @default.
• W20554705 creator A5038028896 @default.
• W20554705 date "2004-01-01" @default.
• W20554705 modified "2023-10-14" @default.
• W20554705 title "Hall Effect Studies of Electron Mobility and Trapping at the SiC/SiO2 Interface" @default.
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• W20554705 doi "https://doi.org/10.1007/978-3-642-18870-1_16" @default.
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