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• W2055796443 abstract "This paper describes the feasibility of software-defined demodulator of DVB-T2 standard using the scalable DSP processor. This paper focuses mainly on the DVB-T2 receiver design and implementation of four major software blocks of the demodulator: FFTs, channel estimator, multi-level de-interleavers and rotated QAM soft-demapper. In particular, 2K-point FFT function is analyzed and mapped on the scalable architecture of coarse-grained reconfigurable array (CGRA) processors resulting 51dB signal to quantization noise ratio (SQNR) performance. The computational burden of frequency interpolator and frequency/cell deinterleavers are greatly reduced with specially designed intrinsics, 30% and 85%, respectively, from the original implementation. The softdemapper for rotated QAM constellation becomes feasible with the latest 1D-MMSE decorrelation method though it is still the most expensive function covering 40% of DTG106 mode. By implementing full chain demodulation software including abovementioned four major functions, it is demonstrated that the software-defined DVB-T2 demodulator is realizable with software on two scalable CGRA processors running at 300MHz." @default.
• W2055796443 created "2016-06-24" @default.
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• W2055796443 date "2013-05-01" @default.
• W2055796443 modified "2023-09-23" @default.
• W2055796443 title "Software-defined DVT-T2 demodulator using scalable DSP processors" @default.
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• W2055796443 doi "https://doi.org/10.1109/tce.2013.6531127" @default.
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