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- W2056247981 abstract "A real-time implementation of bit interleaved coded modulation with iterative decoding (BICM-ID) and a decision feedback equalizer (DFE) receiver is proposed. This receiver is based on processing time optimization, cycle stealing, and efficient internal memory allocation. Moreover, a logarithmic version of symbol-by-symbol maximum a posterior (max-Log-MAP) is introduced with new hardware architecture. ADSP-21364 SHARC Digital Signal Processor (DSP) is used to investigate the proposed implementation in the tank. The experimental results show that the proposed system is attained a stable profile with 30 taps equalizer." @default.
- W2056247981 created "2016-06-24" @default.
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- W2056247981 date "2013-01-01" @default.
- W2056247981 modified "2023-10-16" @default.
- W2056247981 title "Real-time time implementation of iterative decoder and DFE using SHARC processor" @default.
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- W2056247981 doi "https://doi.org/10.1109/iccat.2013.6522039" @default.
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